Cathode ray tube display with means for recording the tube display



Nov. 29, 1966 o. E. HULL. 3,289,196

CATHODE RAY TUBE DISPLAY WITH MEANS FOR RECORDING THE TUBE DISPLAY Filed Deo. 7, 1962 9 sheets-sheet 1 k Kivu,

Nov. 29, 1966 o. EA HULL CATHODE RAY TUBE DISPLAY WITH MEANS FOR RECORDING THE TUBE DISPLAY 9 Sheets-Sheet 2 Filed Dec.

Nov. 29, 1966 o. E. HULL CATHODE RAY TUBE DISPLAY WITH MEANS FOR RECORDING THE TUBE DISPLAY 9 Sheets-Sheet 5 Filed Deo. '7, 1962 f f e .y L C, 5 Il 7 5 /MM 5 2 j f 6 Y f6 lita i114. .c A

Nov. Z9, 1966 o. E. HULL 3,289,196

CATHODE RAY TUBE DISPLAY WITH MEANS FOR RECORDING THE TUBE DISPLAY Filed Dec. 7, 1962 9 sheets-sheet 4 Nov. 29, 1966 o. E. HULL CATHODE RAY TUBE DISPLAY WITH MEANS FOR RECORDING THE TUBE DISPLAY 9 Sheets-Sheet 5 Filed Dec.

Nov. 29, 1966 o. E. HULL 3,289,196

CATHODE RAY TUBE DISPLAY WITH MEANS FOR RECORDING THE TUBE DISPLAY Filed Dec. '7, 1962 9 Sheets-Sheet 6 fw i m w www ww www. Nm uw. www mmm A www SNN Nov. 29, 1966 o. E. HULL 3,289,196

CATHODE RAY TUBE DISPLAY WITH MEANS FOR RECORDING THE TUBE DISPLAY Filed Dec. '7, 1962 9 Sheets-Sheet 7 Nov. 29, 1966 o. E. HULL CATHODE RAY TUBE 3,289,196 DISPLAY WITH MEANS FOR RECORDING THE TUBE DISPLAY 9 Sheets-Sheet 8 Filed Dec.

Nav. 29, 1966 o. E. HULL 3,289,196

CATHODE RAY TUBE DISPLAY WITH MEANS FOR RECORDING THE TUBE DISPLAY Filed Dec. 7, 1962 9 Sheets-Sheet 9 United States Patent 3,289,196 CATHODE RAY TUBE DISPLAY WITH MEANS FOR RECORDING THE TUBE DISPLAY Otis E. Hull, South Pasadena, Calif., assignor to Hull Instruments, Inc., South Pasadena, Calif., a corporation of California Filed Dec. 7, 1962, Ser. No. 244,237 6 Claims. (Cl. 340-324) The present invention relates to read-out systems for converting binary coded data, or other types of coded data, into numeric, or other types of characters to be displayed and recorded.

The present application is a continuation-in-part of copending application Serial No. 173,904, tiled February 19, 1962, and now abandoned, in the name of the present inventor, and assigned to the present assignee.

The invention is particularly concerned with a printer type of read-out system for providing a permanent record of the characters formed thereby in response to the coded input data.

The read-out system of the invention finds utility, for example, in telemetry systems. In a telemetry system it is usual for digital information to be transmitted and recorded on a magnetic tape at the receiving station. The read-out system of the present invention may be used in conjunction with a conventional counter at the receiving station to decode and record the numeric data represented by the information recorded on the magnetic tape.

The read-out system of the invention also nd general utility in conjunction with usual present-day electronic digital computers. The system of the invention may be coupled to the output of a digital computer and is capable of responding to the multi-digit binary output numbers from the computer to produce corresponding decimal characters of numeric or alphanumeric form. When used in conjunction with a digital computer, the extremely high speed capabilities of the system of the ,present invention obviates the need for the usual output bufers in the computer output circuits, and for the usual logic and control circuitry normally associated therewith.

A still further object is to provide such an improved read-out system which is capable of displaying and recording an analog representation of the coded input information, along with the decimal, or other characters displayed and recorded thereby as representative of such input information.

The embodiment of the read-out system of the invention to be described includes what may be termed a high speed, direct read-out printer. T he particular system to be described includes a pair of cathode-ray tubes for forming the characters which are subsequently projected onto a light-sensitive heat-developed paper. The maximum print rate of the system is limited only by the photographic sensitivity and developing time of the paper used. In the embodiment to be described, the pair of cathode-ray tubes is used, rather than a single cathoderay tube, to provide a large-scale display surface for the characters without the attendant requirement of excessively high deflection voltages for the cathode-ray beams in the cathode-ray tubes.

The characters are formed electrically on the face of the cathode-ray tubes in a manner to be described by the controlled deflection of the cathode-ray beams therein. The characters so formed on the face of the cathode-ray tube are optically projected on light-sensitive paper. In the embodiment to be described, this projection is carried out by a lens system commonly referred to as a ber optics lens system. The light-sensitive paper is drawn across the lens system to be exposed by the displayed characters, and the exposed paper is subsequently drawn 3,289,196 Patented Nov. 29, 1966 over a heated platen for developing purposes. The resulting information recorded on the paper constitutes the permanent record of the output information. The mechanical details of the above-mentioned apparatus are more fully described in copending application Serial No. 180,510, led March 19, 1962, in the name of Thomas N. Ross, and assigned to the present assignee.

The system to be described operates in a serial character manner. That is, each binary coded input number applied to the system is stored in an appropriate register, and the binary coded input is subsequently transformed into corresponding blanking signals for the cathode-ray beams of the cathode-ray tubes. The resulting blanking signals are applied in a serial manner to the cathode-ray tubes and in synchronism with a controlled deflection of the cathode-ray beams. The serial application of the blanking signals to the cathode-ray tubes, together with the controlled deflection of the cathode-ray beams, in a manner to be described, causes the characters to ,be`

successively formed on the screens of the cathode-ray tubes. At the completion of the formation of each such character, a signal is transmitted back to the source of the coded input data to inform the source that the systemv is ready to receive the next binary coded input number.

In a second embodiment, the binary coded input information is also fed to a digital-to-analog converter so that the analog signal corresponding thereto may be derived. This latter signal is applied to a cathode-ray tube, galvanometer, or other device, so that a trace of the analog signal may be obtained.

The analog signal trace and the characters successively formed on the screen of the cathode-ray tubes are then projected together onto the light-sensitive paper to obtain a recording of the characters and the analog trace. The characters and analog trace are preferably projected in side-by-side relationship on the recording paper for cornparison purposes.

The features of the invention which are believed to be new are set forth in the claims. Other objects and advantages of the invention will become apparent from a consideration of the following description in conjunction with the accompanying drawings, in which:

FIGURE 1 is a simplified block diagram of a system representative of one embodiment of the present invention;

FIGURE 2 is a more detailed block diagram of the embodiment of FIGURE 1;

FIGURE 3 is a diagram useful in explaining the functioning of the system of FIGURE 2;

FIGURE 4 is a representation of a pair of curves representing the configuration of the horizontal and vertical sweep signals used in the system of FIGURE 2;

FIGURE 5 is a series of curves useful in describing the operation of the system of FIGURE 2;

FIGURE 6 is a circuit representation of a conversion matrix shown in block form in FIGURE 2;

FIGURE 7 is a circuit representation of a clocking matrix shown in block form in FIGURE 2;

FIGURE 8 is a circuit representation of a sawtooth generator shown in block form in FIGURE 2;

FIGURE 9 is a circuit representation of certain blanking circuits shown in block form in FIGURE 1;

FIGURE 10 is a circuit representation of a signal generator shown in block form in FIGURE 2; and

FIGURE 1l is a simplified block diagram of a system representing a second embodiment of the invention and suitable for combined character and corresponding analog trace recordings.

The simplified block diagram of FIGURE 1 includes a source 10 of binary coded data. This source, as explained above, may be a counter positioned in a receiving station of a telemetering system; it may be an elec- 3 tronic digital computer; or it may be any other appropriate source of binary coded data.

The source introduces the binary coded data to a blanking signal generator 12. This generator, as will be explained in more detail subsequently, transforms the coded input signals into appropriate blanking signals. The blanking signals from the generator 12 are applied to a blanking circuit 14 and to a blanking circuit 16.

The blanking circuit 14 is connected to the input electrode of a cathode-ray tube 18, and the blanking circuit 16 is connected to the input electrode of a cathode-ray tube 20. The cathode-ray tubes 18 and 20 may each include the usual beam forming electrodes and deflection plates. A cathode-ray beam is formed in each of the cathode-ray tubes, and the beams in the tubes are blanked at the proper intervals by blanking signals applied to the respective input electrodes by the blanking circuits 14 and 16 The cathode-ray beams in the tubes 18 and 20 are deected horizontally and vertically across the respective faces of the tubes. A liber optic system. 22 is mounted on the face of the tube 18, and a fiber optic system 24 is mounted on the face of the tube 20. As the cathode-ray beam of the tube 18 is deflected across the screen of the tube 18, the resulting light produced by the screen is projected by the optical system 22. Likewise, as the cathode-ray beam in the tube is deected across the screen of the tube, the resulting light produced by the screen is projected by the fiber optic system 24.

The construction of cathode-ray tubes with associated liber optic systems is known to the art, and a detailed description of the tubes 18 and 20 and their associated optical systems 22 and 24 is deemed to be unnecessary herein. A particular type of cathode-ray tube and associated ber optic system ideally suited for use in the system of the present invention is disclosed and claimed, for example, in copending application Serial No. 180,651, led March 19, 1962.

In a manner described more particularly in the copending application Serial No. 180,510, a light sensitive paper 26 is drawn across the faces of the fiber optic systems 22 and 24, so that the characters displayed on the screens of the cathode-ray tubes 18 and 20 may be projected by the respective optic systems 22 and 24 onto the lightsensitive paper 26. The paper 26 is developed by appropriate heating means and it forms a permanent record for the characters.

The system of FIGURE 1 also includes a clocking logic unit 28. A clock input from a suitable clock pulse source 27 is applied to the logic unit 28. A print command is also applied to the unit 28, and the display and recording of each separate character is initiated upon the receipt of the print command from, for example, the computer or other source of the binary coded data.

As each character is displayed by the system of FIG- URE 1, an end of character command is formed, and the latter command is returned to the source of binary coded data 10 to indicate that the system of FIGURE 1 is ready for the next character.

The clocking unit 28 is coupled to a deflection signal forming generator 30 which applies synchronizing signals to the blanking signal generator 12, as will be described. The generator 30 also forms the appropriate dellection signals which are amplified in a horizontal deflection amplifier 32 and in a vertical deflection amplifier 33.

yThe horizontal and vertical deflection plates of the cathode-ray tubes 18 and 20 are connected in parallel with one another. The horizontal deflection signal amplier 32 and vertical deflection signal amplier 33 apply appropriate deflection signals, as will be described, respectively to the horizontal and vertical deection plates of the cathode-ray tubes 18 and 20.

As shown in FIGURE 2, the blanking signal generator 12 of FIGURE 1 includes a plurality of lip-ops 100, 102, 104 and 106. These flip-flops form a register, and the binary coded input data from the source 10 isintroduced in parallel manner to the ip-ops. As indicated, the least significant digit (20) is stored, for example, in the ip-ilop 100, and the most significant digit (23) is stored in the flip-flop 106.

The output terminals of the flip-flops 100, 102, 104 and 106 are connected to a conversion matrix 108. The conversion matrix serves to convert the binary coded data stored in the flip-ops 100, 102, 104 and 106 into corresponding blanking signals for the blanking circuits 14 and 16 of FIGURE l. These blanking signals appear at the output terminals 1-8 of the conversion matrix 108, and they are introduced to a clocking matrix in FIGURE 2.

The clocking matrix 110 of FIGURE 2 serves to synchronize the blanking signals from the conversion matrix 108 with the deecion signals applied to the cathode-ray tubes 18 and 20, so that the blanking signals corresponding to each particular character may be successively introduced in a clocked, serial manner from the clocking matrix 110 to a pair of and gates 112 and 114. The and gate 112 is connected to the blanking circuit 14 of FIGURE 1, and the and gate 114 is connected to the blanking circuit 16 of FIGURE 1.

The clocking logic unit 28 of FIGURE 1, includes in FIGURE 2, a print command flip-flop P and a pair of clock flip-flops C/2 and C/ 4. The print command flipilop P responds to the print command from the source 10 of FIGURE 1 to be set true so as to render the term P true. This ip-op also responds to an end of character signal, to be described, to be set false at the end of the character time Tc (FIGURES 4 and 5 )so as to setV the term P false.

The clock flip-flops C/2 and C/ 4 respond to successive clock input pulses C to be set to their true and false states. These flip-flops are connected as a counter, and the output signal from the clock Hip-Hop C/4 has 1A the frequency of the clock input pulses C, and the outputs from the clock flip-flop C/4 are designated C/4 and m. These outputs are applied to the clocking matrix 110.

The deflection signal forming generator 30 includes an and gate 116 which responds to the signals P and C/ 4, and which is included in a three position counter 118. The three position counter controls a three level staircase generator 120, and the three position counter also controls a flip-flop 122. The and gate 116 applies the term P. C/ 4 to a flip-flop 119, the three position counter 118, and the three position counter 118 in effect divides the frequency of that term by 3.

The counter 118 also includes an and gate 121, a one-shot multivibrator 123 and a further flip-flop 125. The and gate 121 is connected to the one-shot multivibrator which, in turn, is connected to the flip-flops 119 and 125. The flip-flops 119 and 125 are both connected to the staircase generator 120; and these flip-flops are inter-connected and connected to the and gate 121 as` illustrated. The flip-flop 119 applies its outputs C and 7 to the clocking matrix 110; the flip-flop 125 applies its output C to the clocking matrix and the output to the flip-flop 122.

The flip-flop 122 acts as a frequency divider, and the outputs from the llip-op are designated C" and Um. The output (T7 is applied to the clocking matrix 110 and is also applied to the print command flip-flop as the end of character signal.

The term F is also applied to a twenty-two position counter 124, the output of which is applied to a flip-flop 126. The true and false outputs of the latter flip-Flop are applied to the and gates 112 and 114, respectively. The twenty-two position counter 124 also controls a twentytwo level staircase generator 128, the output of which is applied to the horizontal deflection signal amplier 22 of FIGURE 1.

The terms P and C/4 are also applied to a sawtooth generator 130. The sawtooth output signal S.T. which is applied to a pair of and gates 132 and 134. The three level staircase generator 120 develops an output signal S.C. which is applied to a pair lof and gates 136 and 138. Theflip-flop 122 applies the term UT to the and gates 132 and 138; and the flip-flop applies the term C" to the and gates 136 and 134.

The and gates 136 and 132 are connected to an or gate 140 which, in turn, is connected to the staircase generator 128. The and gates 134 and 138 are connected to an or gate 142 which, in turn, is coupled to the vertical deflection signal amplifier 33 of FIGURE 1.

In the formation of each character, the cathode-ray beams in the cathode-ray tube 18 and in the cathode-ray tube 20 are deflected in unison across their corresponding screens, each in accordance with the pattern shown in FIGURE 3. For example, the control is such that deflection signals have a minimum amplitude, the cathoderay beam in each of the cathode-ray tubes assumes the position A in FIGURE 3. As shown in the waveforms of FIGURE 4, the time required to form each character is` designated as Tc. In the first time interval t1, the cathode-ray beam in each cathode-ray tube is deliected horizontally by the sawtooth wave of FIGURE 4A from the position A to the position B in FIGURE 3. The beam is then returned to the position A. Then, in the time interval t2, the vertical deflection signal is stepped, as shown in the waveform of FIGURE 4B, and the beam is again deflected horizontally by the illustrated sawtooth wave of FIGURE 4A from the position C to the position D of FIGURE 3. In like manner, during the interval t3, the beam is deflected from the position E to the position F of FIGURE 3.

The beam is again returned to the position A of FIG- URE 3 and in the interval t4, the beam is deflected vertically from the position A to the position C and from the position C to the position E in FIGURE 3. Likewise, during the time inten/al t5, the beam is deflected vertically from the position G to the position H, and during the interval z5, the beam is deflected vertically from the position B to the position D and from the position D to the position F.

It should be noted that the pattern of deflection of the beam described above in conjunction with FIGURES 3 and 4 occurs in the time interval Tc for the formation of each character. It should also be noted that the deflection elements of both the cathode-ray tubes 18 and 20 of FIGURE l are parallel-connected so that their beams are deflected in unison by the deflection signals of FIGURE 4.

In the formation of each character, the incoming coded binary data is converted and synchronized in a manner such that the beam of the corresponding cathode-ray tube 18 or 20 is blanked and unblanked at the appropriate intervals, so that certain ones of the traces of FIGURE 3 are deleted, in order that the desired characters may be formed.

As shown in FIGURE 2, the incoming clock pulses C are introduced to the clock flip-flop C/ 2, and the output from the clock flip-flop C/2 is applied to the clock flipflop C/4 in the clocking logic unit 28. The clock flipflop C/4 produces the clocking pulses C/4 which have one quarter the repetition frequency of the clock pulses C. The clock pulses C/ 4 have the waveform shown by the curve C/4 in FIGURE 5. It will be observed in FIG- URE 5 that each character interval Tc is composed of six time intervals tl-te. These time intervals are timed by the clock pulses C/4.

Upon the receipt of a print command P by the clocking unit 28 of FIGURE 2, the flip-flop P is set true to enable the and gate 116 and thereby set the three-position counter 118 into operation; and also to cause the sawtooth generator 130 to commence generating sawtooth waves. Then, the clock pulses C/ 4 cause the three-position counter 118 to count, so that the three level staircase generator 130 develops an 6 generator produces thethree level staircase signal designated S.C. in FIGURE 5. The clock pulse C/4 now also causes the sawtooth generator 130 of FIGURE 2 simultaneously to produce the sawtooth signal designated S.T. in FIGURE 5.

As illustrated in FIGURE 5, each cycle of the sawtooth wave S.T. from the sawtooth generator 130 corresponds to one of the time intervals t1-t6, and these sawtooth wave cycles proceed in successive ones of the time intervals t1-t6. Likewise, the staircase signal S.C. from the staircase generator 120 proceeds through its three steps in each group of three successive time intervals corresponding, for example, to the time intervals t1-t3 and tris.

The flip-flop 119 is controlled by the clock pulses C/ 4 during the character interval Tc. It should be pointed out at this time that the print command P marks the beginning and end of the character interval T. The flipflop 119 also responds to pulses from the one-shot multivibrator 123, and as a result, the output pulses from the flip-flop 119 have the waveform illustrated by the curve C in FIGURE 5. Likewise, the flip-flop is controlled by the pulses from the one-shot multivibrator 123 and by the output from the flip-flop 119, so that the flipflop 125 produces an output designated C", the waveform of this latter output also being shown in FIGURE 5.

The flip-flop 122 is controlled by the flip-flop 125 so that its output C" is false during the iirst three time intervals t1, t2, and t3, and is true during the latter three time intervals t4, t5 and t6, of the character time Tc. The waveform for the signal C" is also shown in FIGURE 5. When the flip-flop 122 is set false at the end of the character time Tc, the print command flip-flop P is set false to terminate the character time interval. The end of character command is also sent to the source of the binary data to indicate that the system is ready to receive the next multi-digit binary number. The next character time Tc is not being initiated until a subsequent print command from the source of binary data sets the print command flip-iiop P true.

During the first three intervals t1-t3 of the character time Tc, the flip-flop 122 is false. This causes the and gates 132 and 138 to be enabled. Therefore, during the rst three time intervals t1-t3, the sawtooth wave from the sawtooth generator is applied through the twentytwo level staircase generator 128 to the horizontal deflection signal amplifier 32; and the staircase signal from the three level staircase generator 120 is applied through the and gate 138 to the vertical deflection signal amplifier 33 of FIGURE 1. In this manner, the waveforms illustrated in FIGURES 4A and 4B during the intervals t1, t2 t3 are realized.

At the end 0f the time interval t3, the flip-flop 122 is set true. This causes the and gates 134 and 136 to be enabled for the time intervals t4, t5 and t6. The staircase signal S.C. from the three level staircase generator 120 is now applied through the twenty-two` level staircase generator 128 to the horizontal deflection signal amplifier 32, and the sawtooth signal from the sawtooth generator 130 is applied through the and gate 134 to the vertical deflection signal amplifier 33 of FIGURE 1. Therefore,y the waveforms illustrated in FIGURE 4 as occurring during the time intervals t4, t5 and t6 are realized.

The deflection signal forming generator 30 of FIGURE 2 provides deflection signals to the deflection signal amplifiers 32 and 33, therefore, which are capable of detlecting the cathode-ray beams in the cathode-ray tubes 18 and 20 through the configuration of FIGURE 3 during each character time Tc. The twenty-two position counter 124 is controlled by the flip-flop 122 to cause the twenty-two level staircase generator 128 to rise in voltage through one step at the end of each character time Tc and to remain at the latter voltage step for the duration of the following character time Tc. This latter staircase signal is also applied to the horizontal deflection plates of the cathode-ray tubes 18 and 20, and it serves to move the beams across the cathode-ray tubes in twenty-two discrete horizontal increments. This enables each cathode-ray tube to display twenty-two separate and distinct characters at adjacent positions across its face. The system is controlled, in a manner to be described, so that the characters are successively displayed across the face of one of the cathode-ray tubes and then across the face ofthe other.

The fiip-op 126 is controlled by the twenty-two position counter 124 to control the and gates 112 and 114. The control is such that during the first twenty-two steps of the staircase generator 128 one of the cathode-ray tubes 18 and 20 is rendered inoperative, and during a second twenty-two steps of the staircase generator 128 the other cathode-ray tube is rendered inoperative. This permits a first group of twenty-two characters to be successively displayed at adjacent positions across the face of one of the cathode-ray tubes, and a second group of twenty-two characters to be successively displayed at adjacent positions across the face of the second cathode-ray tube. These characters are recorded in forty-four adjacent positions across the sensitized paper 26 of FIGURE 1. The sensitized paper is then moved vertically to a second row, and a second series of forty-four characters may be recorded on the paper. This results in forty-four columns of different characters on the sensitized paper 26, as the system operates, and as the characters are successively displayed and recorded.

It is evident that for the proper formation of each character, the cathode-ray beam of the particular operative cathode-ray tube 18 or 20 (at any particular character time Tc) must be blanked in synchronism with the deection of the cathode-ray beam in that tube, so that selected ones of the traces of FIGURE 3 may be deleted to form the desired character in each instance.

An examination of FIGURE 3 will reveal that eight distinct traces are identiied. These eight traces correspond to the eight different blanking, or unblanking, signals produced by the conversion matrix 108 of FIG- URE 2. These blanking signals in the particular embodiment under consideration represent different decimal digits of from to 9 when properly synchronized with the deflection signals of FIGURE 4. As shown by the curves 0-9 of FIGURE 5, the diiferent synchronized blanking signals from the clocking matrix 110 have successive true or false congurations during the intervals t1-t6 in accordance with the particular .decimal digit which corresponds to the particular binary coded number applied to the conversion matrix 108.

For example, if the coded binary input number to the conversion matrix 108 is 0, the signals across the output terminals 1-8 of the conversion matrix assume the configuration shown by the wave-form 0 in FIGURE 5. Likewise, the decimal digits 1-9 corresponding to the binary input data are represented by the waveforms designated 1-9 in FIGURE 5.

It will be appreciated that when a waveform, such as the waveform 0 of FIGURE 5 is produced by the conversion matrix 108 and synchronized with the detiection signals in the clocking matrix 110, the traces 2 and 6 of FIGURE 3 will be blanked, so that the display on the face of the corresponding cathode-ray tube will have a rectangular trace, simulating 0. Likewise, when the character to be displayed as 7, the curve 7 of FIGURE 5, will blank the traces 1 and 2, as well as the traces 4, 5 and 6 of FIGURE 3. The resulting illuminated traces 3, 7 and 8 on the screen of the corresponding cathode-ray tube will simulate the number 7. This also applies for the other waveforms of FIGURE corresponding to the other decimal digits.

It will also be appreciated that the conversion matrix 108 may be constructed so that the output blanking signals, when properly synchronized with the cathode-ray tube deection signals, produce blanking in the correi) sponding cathode-ray tube corresponding to letters so that an alphanumeric decoding may be realized.

As noted above, the function of the clocking matrix 110 is to cause the blanking signals from the conversion matrix 108 to be synchronized with the dierent deection signals (FIGURE 4) applied to the corresponding cathode-ray tube 18 or 20, so that the cathode-ray beam in that cathode-ray tube may be blanked at the proper intervals to produce the desired display.

As noted above, the particular embodiment under consideration is capable of printing fortyafour columns of numeric decimal digits. The sensitized paper 26 of FIG- URE 1, for example, may be six inches wide. As noted, the different characters or digits are projected onto the light-sensitive paper, and the exposed paper then passes over a heated platen for development and then appears as the output record. At the completion of each character time To, an end of character command is sent to the data source, and the system is ready to receive the next character.

The circuit details of the conversion matrix 108 are shown in FIGURE 6. The conversion matrix 108 is illustrated as having input terminals 200, 202, 204, 206, 208, 210, 212, and 214. The ip-op is connected to the input terminals 200 and 202 and introduces its outputs 1 and to those respective input terminals. The flip-flop 102 applies its outputs 2 and 2 to the respective input terminals 206; the flip-flop 104 applies its outputs 4 and to the respective input terminals 208 and 210', and the ip-op 106 applies its outputs 8 and 8 to the input terminals 212 and 214. As explained above, the ilip-ops 100, 102, 104 and 106 store during any particular character time Tc the binary coded data to be transformed by theconversi-on matrix 108 into the corresponding character-forming blanking signals.

The matrix 108 includes a plurality of diodes CR1- CR31, and RC1-RC30. The term 1 from the input terminal 200 is applied .to the anodes of the diodes CR1, CR4, CRS and RC15. The term from the input terminal 202 is applied to the anodes of the diodes RC1, RC4, RC9, RC11, CR11 and CRIS.

The term 2 from the input terminal 204 is applied to the anodes of the diodes CR2, RC5, CR9, and RC10. The term 2 from the input terminal 206 is applied to the anodes of the diodes RC3, CRS, CR12, CR14 and RC14. The term 4 from the input terminal 208 is applied to the anodes of the diodes CRS, RC7, RCS, CR10, RC12, RC13 and CR16. The term Jfrom the input terminal 210 is applied to the anodes of the diodes RC2, RC6, CR6 and CR13.

The term 8 from the input terminal 212 is applied to the cathodes of the diodes CR21, CR24, CR31, RC 21, RC25 and RC30. The term 'from the input terminal 214 is applied to the anode of the diode CR7. The cathodes of the diodes CR1 and CR2 are connected to the base of a PNP transistor 216 and to a resistor 218. The transistor 216 is connected as an emitter follower. The emitter of the transistor is connected to a grounded resistor 220, and the collector of the transistor is connected to the negative terminal of a l2-volt direct voltage source. The resistor 218 may have a resistance of 22 kilo-ohms, for example, and the resistor 220 may have a resistance of l0 kilo-ohms. The emitter of the transistor 216 is connected to the cathodes of the diodes CR17, CR22 and CR26.

The cathodes of the diodes CRS and CR4 are con-v nected to a resistor 222. The resistor 222 may have a resistance of 10 kilo-ohms, and it is connected to the negative terminal of the 12-volt direct voltage source. The cathodes of the diodes CRS and CR4 are also connected to the cathodes of the diodes CR18 and CR27.

v The cathodes of the diodes CRS, CR6, CR7 and CRS are connected to a resistor 224. The resistor 224 may have a resistance of 22 kilo-ohms, and it is connected 9 to the negative terminal lof the 12-volt direct voltage source. These cathodes are also connected to the output terminal 6 of the conversion matrix 106.

The cathodes of the diodes CR9 and CR10 are connected to a resistor 226. The resistor 226 may have a resistance of kilo-ohms, and it is connected to the negative terminal of the l2-volt direct voltage source. These cathodes are also connected to the cathodes of the diodes CR19 and CR28.

The cathodes of the diodes CR11 and CR12 and CR13 are connected to a resistor 228. This latter resistor may have a resistance of 22 kilo-ohms, and it is connected to the negative terminal of the l2-volt direct voltage source. These cathodes are also connected to the cathode of the diode CR29.

The cathodes of the diodes CR14, CR and CR16 are connected to a resistor 230. This resistor may have a resistance of 10 kilo-ohms, and it is connected to the negative terminal of the 12-volt direct voltage source. These cathodes are also connected to the cathodes of the diodes CR and CR30.

The cathodes of the diodes RC1 and RC2 are connected to a resistor 232, the cathodes of the diodes RC3 and RC4 are connected to a resistor 234. The resistors 232 and 234 may each have a resistance of 22 kilo-ohms, and each are connected to the negative terminal of the 12-volt direct voltage source.

The cathodes of the diodes RC5 and RC6 are connected to a resistor 236, and the cathodes of the diodes RC7 and RCS are connected to a resistor 238. Each of these resistors may have a resistance of l() kilo-ohms, and each is connected to the negative terminal of the l2-volt direct voltage source.

The cathodes of the diodes RC9 and RC1() are connected to a resistor 240, the cathodes of the diodes RC11 and RC12 are connected to a resistor 242, and the cathodes of the diodes RC13, RC14 and RCIS are connected to a resistor 244. Each of these resistors may have a resistance of 22 kilo-ohms, and each is connected to the negative terminal of the 12-volt direct Voltage source.

The cathodes of the diodes RC1 and RC2 are connected to the base of a PNP transistor 246. The collector of the transistor 246 is connected to the negative terminal of the 12-volt direct voltage source, and the emitter of the transistor is connected to a 10 kilo-ohmgrounded resistor 248. The transistor 246 is connected as' an emitter follower, and its emitter is connected to the cathodes of the diodes CR20, CR23, RC16 and RC26.

The cathodes of the diodes RC3 `and RC4 are connected to the cathode of the diode RC18. The cathodes of the diodes RC5 and RC6 are connected to the cathodes of the diodes RC22 and RCZS. The cathodes of the diodes RC7 and RCS are connected to the cathodes of the diodes RC19 and RC23.

The cathodes of the diodes RC9 and RC1() are connected to the emitter of a PNP transistor 250. The collector of the transistor 250 is connected to the negative terminal of the l2-volt direct voltage source. The emitter of the transistor is connected to a grounded l0 kiloohm resistor 252. The transistor 250 is connected as an emitter follower, and its emitter is connected to the cathodes of the diodes RC17, RC24, and RC27.

The cathodes of the diodes RC11 and RC12 are connected to the cathode of the diode RC20. The cathodes of the diodes RC13, RC14 and RC15 are connected to the cathode of the diode RC29.

The anodes of the diodes (3R17, CR18, `CR19, CR20 and CR21 are all connected to a resistor 254. The resistor 254 may have a resistance of 47 kilo-ohms, and it is connected to ground. These anodes are also connected to the output terminal 3.

The anodes of the diodes CR22, CR23, CR24 and CR25 are connected to a resistor 256. The resistor 256 may have a resistance of 47 kilo-ohms, and it is grounded.

10 These latter anodes are also connected to the output terminal 8.

The anodes of the diodes CR26, CR27, CR28, CR29, CR30 and CR31 are all connected to a resistor 258. The resistor 238 may have a resistance of 47 kilo-ohms, and it is grounded. The anodes of these diodes are also connected to the output terminal 7.

The anodes of the diodes RC16 and RC17 are connected to a resistor 260; the anodes of the diodes RClS, RC19, RC20 and RC21 are connected to a resistor 262; the -anodes of the diodes RC22, RC23, RC24, and RCZS are connected to a resistor 264; and the anodes of the diodes RC26, RC27, RC28, RC29 and RC30 are connected to a resistor 266. The resistors 260, 262, 264 and 266 are all grounded, and each may have a resistance of 47 kilo-ohms. The resistor 260 is connected to the output terminal 4, the -resistor 262 is `connected to the output terminal 5, the resistor 264 is connected to the output terminal 2, and the resistor 266 is connected to the output terminal 1.

The conversion matrix 108 operates as a usual diode matrix to convert the outputs from the flip-flops 100, 102, 104 and 106 into the character-forming blanking output signals, such as shown by the curves 0-9 of FIGURE 5. For example, when all the Flip-flops 100, 102, 104 and 106 are false to represent the binary equivalent of 0, thek diode matrix of FIGURE 6 causes the output signals at the terminals 1, 3, 4, 5, 7 and 8 to be low, and at the terminals 2 and 6 to be high. This provides the waveform 0 of FIGURE 5 which, in the manner described above, when synchronized with the deilection signals causes the corresponding cathoderay tubes 10 or 20 to display the numeral 0. In like manner, when the ilip-iiop is true, and' the other flip-flops 102,v 104 and 106 are false, so as to represent the binary coded equivalent of the decimal digit 1, the conversion matrix 108 causes the blanking signal outputs at the output terminals 1, 2, 3, 4, 5, 7 and 8 to be high, and the output at the terminal 6 to be low. This provides a blanking for all the traces of the diagram of FIGURE 3, with the exception of the number 6 trace, so that the number 1 is displayed. In like manner, the conversion matrix 108 responds to the different states of the ipliops 100, 102, 104 and 106 to provide the other blanking signal equivalents at the output terminals 1-8.

An appropriate circuit for the clocking matrix 110 is shown in FIGURE 7. The circuit includes an or gate 301 comprised of a plurality of diodes 301, 302, 304, 306, 308, 310, 312 and 314. The anodes of these diodes are all connected to a grounded resistor 316, which may have a resistance of 47 kilo-ohms, and to the and gates 112 and 114 of FIGURE 2.

The clocking matrix of FIGURE 7 also includes a plurality of and gates 318, 320, 322, 324, 326, 328, 330 and 332. The and gates are connected to respective resistors 334, 336, 338, 340, 342, 344, 346 and 348. Each of these resistors may have a resistance of 22 kilo-- ohms, and the resistors are connected to the negative terminal of the 12 volt direct voltage source. The and gates 318, 320, 322, 324, 326, 328, 330 and 332 are also connected to the cathodes of respective ones of the diodes 301, 302, 304, 306, 308, 310, 312 and 314 of the or gate 300.

The clocking matrix 110 responds to the different signals from the deliection signal forming generator 30 of FIGURE 2. These signals include the signals C/ 4, C', C and C" described above and illustrated in FIG- URE 5.

The dilerent and gates 318, 320, 322, 324, 326, 328, 330 and 332 of the clocking matrix 110 respond to the different signals C/ 4, C', C" and C" (and to the complements thereof m, n and W) so that the output terminal 1 of the conversion matrix 108 may be effectively connected to the and gates 112 and 114 in the t1 time intervals; so that the output terminal 2 of the conversion matrix 108 may be effectively connected to the and gates during the t2 time interval; so that the output terminal 3 of the conversion matrix may be connected to the and gates in the time interval t3; so that the output terminal 4 of the conversion matrix may be etectively connected to the and gates during the rst half of the time interval t4, and so that the output terminal 5 of the conversion matrix may be effectively be connected thereto during the latter half of the interval t4; so that the output terminal 6 of the conversion matrix may be effectively connected to the and gates during the time interval t5; so that the output terminal 7 of the conversion matrix may be effectively connected to the and gates during the first half of the time interval t6; and so that the output terminal 8 of the conversion matrix 108 may be effectively connected to the and gates 112 and 114 during the latter half of the time interval t6.

The above-mentioned effective connections are made at the proper time intervals tl-ts by the clocking matrix 110, by the application to the different and gates 318, 320, 322, 324, 326, 328, 330, 332 of the signals C/4, C', C and C in the manner illustrated in FIGURE 7. As illustrated in FIGURE 7, the signals C/4, C and C" are applied to the and gate 318. These signals cause the and gate 318 to be enabled during the latter half of the time interval t6, so that the signal at the output terminal 8 of the conversion matrix 108 is applied during that time interval through the or gate 300 to the and gates 112 and 114 of FIGURE 2.

Likewise, the signals /TI, C and C are applied to the and gate 320 to cause the and gate 320 to be enabled during the rst half of the time interval t6. This permits the signal appearing at the output terminal 7 of the conversion matrix108 to be applied through the or gate 300 to the and gates 112 and 114 of FIGURE 2 during the time interval t6.

The signals C', W, and C" are applied to the and, gate 322. These signals enable the and gate 322 during the time interval t5. This permits the signal at the output terminal 6 of the conversion matrix 108 to be applied through the or gate 300 to the and gates 112 and 114 at that time interval.

The signals C/4, F and C" are applied to the and gate 324. These signals enable the and gate 324 during the latter half ofthe t4 interval. This permits the signal appearing at the output terminal 5 of the conversion matrix 108 to be applied to the and gates 112 and 114 of FIGURE 2 at that time.

The signals C /4, C and C" are applied to the and gate 326. These signals enable the and gate 326 during the rst half of the t4 interval. This allows'the output signal appearing at the terminal 4 of the conversion matrix 108 to be applied to the and gates 112 and 114 during that interval.

The signals C and are applied to the and gate 328. These signals enable the and gate 328 during the time interval t3. This permits the signal appearing at the output terminal 3 of the conversion matrix 108 to be applied through the or gate 300 to the and gates 112 and 114 of FIGURE 2 during that interval.

The signals C', and lare applied to the and gate 330. These signals enable the and gate 330 during the t2 time interval. This permits the signal appearing at the output terminal 2 of the conversion matrix 108 to be applied through the or gate 300 to the and gates 112 and 114 during that interval.

Finally, the signals '(57, W and are applied to the and gate 332. These latter signals enable the and gate 332 during the t1 time interval. This permits the signal appearing at the output terminal 1 of the conversion matrix 108 to be applied to the and gates 112 and 114 during the t1 time interval.

Therefore, by the action of the clocking matrix 110, the signals at the output terminals of the conversion matrix 108 are applied to the blanking circuits of the cathoderay tubes 18 and 20 at the proper intervals to blank or unblank the cathode-ray beams in the tubes in synchronism with the deflection of the cathode-ray beams so that the desired characters may be successively displayed on the faces of the tubes and recorded on the sensitized paper 26 of FIGURE l.

The circuit details of the sawtooth generator of FIGURE 2 are shown in FIGURE 8. The circuit of FIG- URE 8 includes an input terminal 399 to which the print command P is applied. This input terminal is connected to a variable resistor 400 which may, for example, have a resistance of 200 kilo-ohms.

The resistor 400 is connected to a grounded capacitor 402 and to the collector of a PNP transistor 404. The capacitor 402 may have a capacity of 1200 micro-microfarads, for example, when the clock frequency is 100 kilocycles. The transistor 404 may be of the type presently designated 2N404. The emitter of the transistor 404 is grounded, and the collector is further connected to the base of a transistor 406. The transistor 406 may also be of the type presently designated 2N404.

The clock pulses C/4 are applied to an input terminal 408. The input terminal 408 is connected to a capacitor 410 which, in turn, is connected to a resistor 412. The capacitor 410 may have a capacity of 33 micro-microfarads. The resistor 412 may have a resistance of 33 kilo-ohms, and it is shunted by a capacitor 414 which may, for example, have a capacity of 100 micro-microfarads.

The resistor 412 is connected to the base of a transistor 416. This transistor may be of the type presently designated 2N711. The emitter of the transistor 416 is grounded, and the base is further connected to a resistor 418. The resistor 418 may have a resistance, for example, of kilo-ohms, and it is connected to the positive terminal of the l2 volt direct voltage source.

The collector of the transistor 416 is connected to a resistor 420 and to a resistor 422. The resistor 420 may have a resistance of 3.9 kilo-ohms, and it is connected to the negative terminal of the 12 volt direct voltage source. The junction of the capacitor 410 and resistor 412 is also connected to the negative terminal of the l2 volt direct voltage source through a resistor 422. The resistor 422 may, for example, have a resistance of 33 kilo-ohms.

The resistor 422 may have a resistance, for example, of 2.2 kilo-ohms, and it is connected to the base of the transistor 404. The base of the transistor 404 is also connected to a resistor 424. The latter resistor may, for example, have a resistance of 4.7 kilo-ohms, and it is connected to the positive terminal of the l2 volt direct voltage source.

The collector of the transistor 406 is connected to the negative terminal of the 12 volt direct voltage source. The emitter of the transistor is connected to a grotmded resistor 426. The resistor 426 may, for example, have a resistance of l0 kilo-ohms. The emitter of the transistor 406 is also connected to a resistor 428 and to a resistor 430. The resistor 428 has a resistance, for example, of 100 kilo-ohms, and the resistor 430 has a resistance, for example, of l5 kilo-ohms. The resistor 428 is connected to the positive terminal of the 12 volt direct voltage source, and the resistor 430 is shunted by a capacitor 432. The capacitor 432 may have a capacity of l0() micromicrofarads.

The resistor 430 is connected to the base of a transistor 434. The transistor 434 may be a PNP transistor, of the type presently designated 2N404. The base of the transistor 434 is connected to a resistor 436. The resistor 436 may, for example, have a resistance of 100 kilo-ohms, and it is connected to a variable resistor 438. The resistor 438 may, for example, have a resistance of 500 kiloohms, and it is connected to the positive terminal of the 12 volt direct voltage source.

The collector of the transistor 434 is connected to a resistor 440 and to a resistor 442. The resistor 442 may, for example, have a resistance of 75 kilo-ohms, and it is connected back to the base of the transistor 434. The resistor 440 may, for example, have a resistance of 4.7 kilo-ohms, and it is connected to the negative terminal of the 12 volt direct voltage source. The collector of the transistor 434 is also connected to an output terminal designated STI, The sawtooth wave S.T. shown in FIG- URE is developed at that output terminal, and this sawtooth wave is applied to the and gates 132 and 134 of FIGURE 2.

The sawtooth generator of FIGURE 8 is a transistorized ramp signal generator. The application of the signal P to the input terminal 399 causes the capacitor 420 gradually to charge from Zero towards a positive value. The charging of the capacitor 420 continues until the occurrence of the next clock pulse C/ 4 at the input terminal 404. The occurrence of the next clock pulse causes the transistor 404 to become conductive, so that the capacitor 420 is rapidly discharged. The resulting sawtooth wave across the capacitor 402 is applied to the emitter follower circuit of the transistor 406, and the sawtooth wave from the emitter follower is amplied by the amplier circuit of the transistor 434.

The circuit details of the blanking circuits 14 and 16 of FIGURE 1 are shown in detail in FIGURE 9. The blanking signal from the and gate 112 of FIGURE 2 is applied to an input terminal 500, and the blanking signal from the and gate 114 of FIGURE 2 is applied to the input terminal 502. The vertical deilection signal from the or gate 142 of FIGURE 2 is applied to an input terminal 504, and the horizontal deflection signal from the staircase generator 128 of FIGURE 2 is applied across a pair of input terminals 506 and 508.

The input terminal 500 is applied to the control grid of a pentode 510. This pentode may be of the type designated 6AU6. The cathode of the pentode 510 is grounded, and its screen electrode is connected to the resistor S12. The resistor 512 may, for example, have a resistance of 33 kilo-ohms, and it is connected to the positive terminal of a 300 volt direct voltage source. The suppressor electrode of the pentode 510 is also grounded, and the anode of the pentode is connected through a choke coil 514 to a resistor 516. The choke coil 514 may, for example, have an inductance of 2.5 millihenries, and the resistor may have a resistance of 6.8 kilo-ohms. The resistor 516 is also connected to the positive terminal of the 300 volt direct voltage source. The junction of the inductance coil 514 and resistor 516 is connected to a resistor 518. The resistor 518 and the anode of the pentode 510 are both connected to a coupling capacitor 520.

The input terminal 502 is connected to the control grid of a pentode 522. The pentode 522 may also be a 6AU6 pentode, and it is connected in a manner similar to the connections of the pentode 510. The anode of the pentode 522 is connected to a coupling capacitor 524. The coupling capacitors 520 and 524 may each have a capacity of .0047 microfarad. The capacitor 520 is connected to the junction of a resistor 526 and a resistor S28. The resistor 526 has a resistance of 470 kilo-ohms, and it is shunted by a diode 530. The resistor 528 has a resistance, for example, of 47 kilo-ohms, and it is shunted by a capacitor 532. The capacitor 532 may have a capacity of .0l microfarad. The resistor 528 is connected to the control grid of the cathode-ray tube 18.

The coupling capacitor 524 is connected to the junction of a pair of resistors 534 and 536. The resistors may have the same respective values as the resistors 526 and 528. The resistor 534 is shunted by a diode 538, and the resistor 536 is shunted by a capacitor 540. The capacitor 540 may have a capacity of .01 microfarad. The resistor 536 is connected to the control grid of the cathode-ray tube 20.

The circuit of FIGURE 9 includes a direct voltage source 541 having a value, for example, of 3 kilovolts. The positive terminal of the source is grounded, and the negative terminal is connected to a grounded capacitor 542 and to the movable arm of a balancing potentiometer 544. The capacitor 542 may, for example, have a capacity of 0.5 microfarad. The potentiometer 544 is connected to a resistor 546 and to a resistor 548. Each of these resistors may have a resistance, for example, of 470 kilo-ohms. The resistor 526 is connected to one side of the potentiometer 544, and the resistor 534 is connected to the other side of the potentiometer.

A brightness control potentiometer 550 is connected across the resistor 548. The potentiometer 550 may, for example, have a resistance of 250 kilo-ohms. The movable arm of the brightness control potentiometer 550 is connected to the cathodes of the cathode-ray tubes 18 and 20. A capacitor 552 is bridged between the movable arm of the potentiometer 550 and one of the fixed contacts of the potentiometer. This capacitor may, for eX- ample, have a value of .1 microfarad.

The input terminal 504 is connected to a potentiometer 560. This potentiometer may have a resistance of 10 kilo-ohms, and its other fixed contact is grounded. The movable arm of the potentiometer 560 is connected to the control grid of a pentode 562. The pentode 562 may be of the type designated 6CL6, and it is connected as a vertical deection signal ampliier.

The cathode of the pentode 562 is connected to a grounded resistor 564. The resistor 564 may, for example, have a resistance of 820 ohms. The suppressor grid of the pentode 562 is grounded, and the screen grid is connected through a resistor 566 to the positive terminal of the 300 volt direct voltage source. The resistor 566 may, for example, have a resistance of 82 kilo-ohms. The anode of the pentode 562 is connected to a resistor 56S. The resistor 568 may, for example, have a resistance of 10 kilo-ohms, and it is connected to the positive terminal of the 30() volt direct voltage source. The anode of the pentode 562 is also connected to one of the vertical deflection plates of the cathode-ray tube 18 and to one of the vertical deection -plates of the cathode-ray tube 20.

The input terminal 506 is connected to a resistor 570 which is shunted by a capacitor 572. The resistor 570 may have a resistance of 22 kilo-ohms, and the capacitor 572 may have a capacity of 10 micro-microfarads. The resistor 570 is connected to the control grid of a pentode 574. The pentode 574 may be of the type designated 6CL6.

The input terminal 508 is connected to a resistor 576 which is shunted by a capacitor 578. The resistor 576 may have a resistance of 22 kilo-ohms, for example, and the capacitor 578 may have a capacity of 10 micromicrofarads. The Iresistor 576 is connected to t-he control grid of a pentode 580. rl'he pentode 574 and the pentode 580 are connected as a horizontal deflection signal amplifier.

The cathode of the pentode 574 is connected to a potentiometer 582, and the cathode of the pentode 580 is connected to the opposite side of the potentiometer 582. The suppressor grids of the pentodes 574 and 580 are both connected to the negative terminal of the 12 volt direct voltage source. The cathodes of the pentodes are also connected to the negative terminal of the 12 volt direct voltage source through respective 1 kilo-ohm resistors 586 and 588. The movable arm of the potentiometer 582 is connected to the cathode of the pentode 580.

The screen electrodes of the pentodes 574 and 580 are both connected to a resistor 590. The resistor 590 may, for example, have a resistance of 15 kilo-ohms, and it is connected to the positive terminal of the 300 volt direct voltage source. A potentiometer 592 is connected to the control grids of the pentodes 574 and 580. The potentiometer 592 may, for example, have a resistance of kilo-ohms, and its movable arm is grounded.

The anodes of the pentodes are connected through respective inductance coils 594, 596 and through respective resistors 598 and 600 to the positive terminal of the 300 volt direct voltage source. The inductance coils may each have an inductance of 2.5 millihenries, and the resistors may each have a resistance of 7 kilo-ohms. The anode of the pentode 574 is connected to one of the horizontal deflection plates of the cathode-ray tube 18 and to one of the horizontal deflection plates of the cathode-ray tube 20. The anode of the pentode 580 is connected to the other horizontal deilection plate of the cathode-ray tube 18, and to the other horizontal deflection plate of the cathode-ray tube 20.

The brightness control potentiometer 550 is connected to a resistor 602. The resistor 602 may, for example, have a resistance of 470 kilo-ohms, and it is connected to a focus control potentiometer 604. The focus control potentiometer may have a resistance of 500 kilo-ohms, and its movable arm is connected to the focus electrodes of the cathode-ray tubes 18 and 20.

The potentiometer 604 is connected through a series of resistors 606, 608, 610 and 612 to ground. The resistor 606 may have a resistance of 470 kilo-ohms, the resistor 608 may have a resistance of 560 kilo-ohms, the resistor 610 may have a resistance of 470 kilo-ohms, and the resistor 612 may have a resistance of 560 kiloohms.

The cathode-ray tubes 18 and 20 include further electrodes which are connected to the movable arm of an astigmatism control potentiometer 614. The potentiometer 614 and further potentiometers 616 and 618, are connected between the positive terminal of the 300 volt direct voltage source and ground. Each of these potentiometers may have a resistance of 250 ohms. The movable arm of the potentiometer 616 is connected to the other vertical plate of the cathode-ray tube 18, and

this potentiometer serves as a manual control for the vertical positioning of the beam in the cathode-ray tube 18. The movable arm of the potentiometer 618 is connected to the other vertical dellection electrode of the cathode-ray tube 20, and this latter potentiometer serves as a manual adjustment for the vertical position of the beam in the cathode-ray tube 20.

Both the cathode-ray tubes 18 and 20 are normally Vblanked by the voltage source 541. However, when the and gate 112 of FIGURE 2 is enabled, the unblanking signals passed through that and gate cause the cathoderay tube 18 to be selectively unblanked, in the manner described above.

Likewise, when the and gate 114 of FIGURE 2 is enabled, the unblanking signals passed through that and gate cause the cathode-ray tube 20 to be selectively unblanked in the described manner.

The brightness of the reproduced characters may be controlled by the brightness control potentiometer 550. The cathode-ray tubes may be balanced by adjustment of the potentiometer 544. The potentiometer 614 controls astigmatism in the reproduced characters. The potentiometers 616 and 618 control the initial undeilected vertical position of the beams in the cathode-ray tubes 18 and 20. As mentioned above, it is desirable that the initial condition of the beams be adjusted so that they assume the point A in the representation of FIGURE 3 for their undeflected position, at the beginning of each character time Tc.

The vertical deection signal from the or gate 142 lof FIGURE 2 is ampliiied in the vertical deflection signal amplifier of the pentode 562 and applied to the vertical deflection plates of the cathode-ray tubes 18 and 20. The horizontal deection signals are amplified by the circuits of the pentodes 574 and 580, and applied to the horizontal deflection plates of the cathode-ray tubes. These deflection signals have the waveform discussed above, and are Synchronized with i116 @bows-described unblanking signals 16 so that the desired characters may be reproduced on the screens of the cathode-ray tubes 18 and 20.

The staircase generator of FIGURE 2 is shown in circuit detail in FIGURE 10. It will be understood that the 22-level staircase generator 128 may be similarly constructed.

The staircase generator 120 includes a pair of input terminals 700 and 702. The input terminal 700 receives the term C from the ilip-op 119 of FIGURE 2, and the input terminal 702 receives the term T from the flip-op of FIGURE 2.

The input terminal 700 is connected to a resistor 704 which, in turn, is connected to the |base of a transistor 706. The input terminal 702 is connected to a resistor 706 which is connected to the base of a resistor 708 which, in turn, is connected to the base of a transistor 710. The base of the transistor 706 is connected through a resistor 712 to the positive terminal (+V) of a source of direct current exciting potential. The base of the transistor 710 is connected through the resistor 714 to the positive terminal of that source. The emitters of the transistors 706 and 710 are grounded.

The collector of the transistor 706 is connected through a resistor 716 to the negative terminal (-V) of thev direct current source, and to a resistor 718. The collector of the transistor 710 is connected through a resistor 720 to the negative terminal (-V) and to a resistor 722. The resistor 718 is shunted by a diode 724, and the resistor 722 is shunted by a diode 726.

A resistor 728 is connected to the resistors 718 and 722. The resistor 728 is further connected to a grounded resistor 730. The junction of the resistors 718 and 728 is connected to a grounded resistor 732. The junction of the resistors 728 and 730 is connected to an output terminal 734, at which the staircase signal S.C. appears. This output terminal, as described in conjunction with FIGURE 2, is connected to the and" gates 136 and 138. The resistors 716, 718, 720, 722, 728, 730, and 732 all have equal value.

Thte circuitry of FIGURE 10 is a usual ladder-adder network. The transistors 706 and 710 are controlled by the Iiip-flops 119 and 125 in a manner such that during the rst time interval of each cycle the transistor 706 is conductive and the transistor 710 is non-conductive, during the second time interval of each cycle the transistor 706 is non-conductive and the transistor 710 is conductive, and during the third time interval of each cycle both the transistors 706 and 710 are conductive.

During the iirst time interval the transistor 706 is non-conductive and the transistor 710 is conductive. The non-conductivity of the transistor 706 establishes the junction X of the resistors 716, 718 at the -V potential level. This causes the diode 724 to become conductive, and a current lows through the resistors 732 and 736 to establish a potential of -V/2 at the junction Z of the resistors 718 and 732. A current also iiows through the resistors 728 and 730 to establish a potential -V/4 at the output terminal 734. During this irst time interval, the conductivity of the transistor 710 establishes the junction Y between the resistors 720 and 722 at ground potential, so that there is no current ow through the resistors 722 or 730 due to this transistor.

During the second time interval, the conductivity of the transistor 706 establishes the junction X of the resistors 716 and 718 at ground potential, so that there is no current flow through t-he resistors 718, 728 or 732. The non-conductivity of the transistor 710 during this rst time interval establishes the junction Y of the resistors 720 and 722 at the -V potential level. This causes the diode 726 to become conductive and a current to flow through the resistor 730. This establishes an output voltage -V/2 at the output terminal 734.

During the third time interval of each cycle, both of the transistors 706 and 710 are rendered non-conductive. This means that there is no current flow through the neti7 Work, and the output terminal 732 is established at or ground potential.

Therefore, in the described manner, the potential at the output terminal 734 rises in three steps from -V/4 to -V/2 to zero during each cycle. The particular waveform S.C. is shown in t-he curves of FIGURE 5, and described above.

Portions of the system shown in FIGURE l1 are similar to the system of FIGURE 1, and like elements have been identified by the same numerals.

As in the system of FIGURE 1, the source in FIGURE l1 introduces binary coded data to the blanking signal generator 12. The generator 12, as before, transforms the coded input signals into appropriate blanking signals.

In the formation of each character, the cathode-ray beam in the cathode-ray tube is deflected across the screen of the tube. The incoming coded binary data from the source 10 is converted and synchronized in the described manner such that the beam ofthe cathode-ray tube 18 is blanked and unblanked at appropriate intervals, in order that the desired characters may be formed.

In the manner described, the cathode-ray tube is controlled to display, for example, twenty-two separate and distinct characters at adjacent positions across its face.

In the system of FIGURE 11, the binary coded data form the source 10 is also applied to a digital-analog converter 800. The converter 800 may be of any known appropriate type, and it operates in known manner to convert the binary coded data from the source 10 into corresponding analog signals.

The counter 124 of FIGURE 2 is connected to a twenty-two level staircase generator 802. The output from the generator 802 and the output from the converter 800 are applied to a summing network 804 which in turn is connected to a horizontal deflection signal amplifier 806.

The horizontal deflection signal amplifier 806 is connected to the horizontal deflection plates of the cathoderay tube 20. The cathode-ray tube 20 is excited, in the system of FIGURE 1l, so that its cathode-ray beam has constant intensity. The beam in the tube 20 is deflected horizontally only.

In the system of FIGURE 1l, the various characters are reproduced on the screen of the cathode-ray tube 20 in the manner described above. At the same time the cathode-ray tube 20 reproduces the analog signals corresponding to the different characters and which appear as traces on the sensitized paper 26.

The system of FIGURE 11, therefore, is capable of presenting a record not only of the decimal characters, or the like, corresponding to the received binary coded data, but also curves representative of the equivalent analog quantities.

It will be appreciated that the combined read-out system of FIGURE ll can be modified and extended to embrace combined analog and facsimile representations, combined decimal character and facsimile representations, and so on.

It will also be appreciated that the analog quantities can be reproduced by a galvanometer, or the like, instead of the cathode-ray tube 20.

The invention provides, therefore, an improved readout system for converting binary coded data, or other types of coded data, into numeric or other types of characters. The improved system of the invention includes cathode-ray tubes and associated circuitry which responds to the input data to cause the corresponding characters to be displayed on the faces of the cathoderay tubes. The displayed characters are projected onto a sensitized recording paper, so that a permanent record may be made.

While a particular embodiment of the invention has been described, modifications may be made, and it is intended in the claims to cover all such modifications as fall within the scope of the invention.

What is claimed is:

1. A read-out system including: input circuit means for receiving input signals representative of certain data; cathode-ray tube means including at least one viewing screen, means for forming a cathode-ray beam in the tube and means for deflecting the beam across the viewing screen; means coupled to said beam deflecting means for producing deflection signals for deflecting the beam across said viewing screen in a predetermined manner to enable a series of predetermined characters to be displayed on the viewing screen; means coupled to said input circuit means and to said deflection signal producing means for controlling the intensity of said beam in accordance with said input signals and in synchronism with said deflection signals selectively to cause different ones of said characters to be displayed on said screen; converter circuit means coupled to said input circuit means for converting said input signals into corresponding analog signals; and display means coupled to said converter circuit means and responsive to said analog signals therefrom for displaying representations corresponding thereto.

2. A read-out system including: input circuit means for receiving binary coded input signals representative of binary coded data; cathode-ray tube means including at least one viewing screen, means for forming a cathoderay beam in the tube, and means for deflecting the beam across the viewing screen; circuit means for cyclically producing a predetermined series of deflection signals and coupled to said beam dellecting means for deflecting the cathode-ray beam across the viewing screen in a predetermined pattern to enable a series of predetermined characters to be displayed on the viewing screen; further circuit means coupled to said input circuit means and to said deflection signal producing circuit means for causing the cathode-ray beam to be blanked at particular intervals in each of the deflection cycles thereof in accordance with said binary input signals and in synchronism with said deflection signals selectively to cause different ones of said characters to be displayed on said screen; converter circuit means coupled to said input circuit means for converting said binary coded input signals into corresponding analog signals; and display means coupled to said converter circuit means and responsive to said analog signals therefrom for displaying representations corresponding thereto.

3. The read-out system of claim 2 in which said display means comprises a cathode-ray tube having a display screen disposed adjacent said first mentioned viewing screen for displaying said analog representations adjacent the corresponding characters displayed on said first mentioned viewing screen.

4. A read-out system including: register means for receiving binary input signals representative of binary coded data and including a plurality of flip-flops for storing said data; cathode-ray tube means including a viewing screen, means for forming a cathode-ray beam in the tube, horizontal and vertical deflection means for deflecting the cathode-ray beam across said viewing screen; circuit means for producing a predetermined series of deflection signals in each of a plurality of successive deflection cycles, each of said deflection cycles including six time intervals. said circuit means being coupled to said beam deflection means for dellecting the cathode-ray beam across said viewing screen in a predetermined pattern to enable a series of particular characters to be displayed on said viewing screen, and said circuit means including saw-tooth signal generating means and step signal generating means, with means for coupling said saw-tooth signal generating means to said horizontal deflection means and said step signal generating means to said vertical deflection means during the first three of said six time intervals of each deflection cycle and for coupling said saw-tooth signal generating means to said vertical deflection means and said step signal generating means to said horizontal deection means during the second three of said six time intervals of each deection cycle; a conversion matrix network coupled to said register means for producing a plurality of beam blanking signals in response to the data stored in said ip-ops, synchronizing circuit means coupled to said conversion matrix network and to said deflection signal producing means and responsive to said beam blanking signals for causing the cathode-ray beam to be blanked at particular intervals in each of the deilection cycles thereof in synchronism with said deflection signals selectively to cause diierent ones of said characters to be displayed on said screen; sensitized paper means disposed adjacent said viewing screen for recording the characters displayed on said viewing screen; and optic ber means interposed between said viewing screen and said sensitized paper means for transferring the characters displayed on said viewing screen to said sensitized paper means.

5. The read-out system of claim 4 in which said sawtooth signal generating means produces a saw-tooth signal during each of the six time intervals of each deection signal and in which said step signal generating means produces a three-step signal during each three 20 successive ones of said six time intervals of each deflection cycle.

6. The read-out system of claim 4 in which said deflection signal producing means includes a further step signal generating means coupled to said horizontal deilection means for causing the cathode-ray beam to be deflected from one position to another across said screen for each of said successive deection cycles.

References Cited by the Examiner UNITED STATES PATENTS 2,766,444 10/ 1956 Sheftelman.

2,807,663 9/1957 Young 340-3241 2,811,665 10/1957 McNaney 340-3241 2,875,951 3/ 1959 Schreiner B4G-324.1 2,931,022 3/1960 Triest S40-324.1 2,947,813 8/1960 Valensi 178-15 2,957,104 10/ 1960 Roppel S40-324.1 2,962,625 11/1960 Berwin et al. 340-3241 3,104,387 9/1963 Loshin 340-324.1 3,138,663 6/1964 McNaney 340-3241 NEIL C. READ, Primary Examiner. H. I. PITTS, Assistant Examiner. 

1. A READ-OUT SYSTEM INCLUDING: INPUT CIRCUIT MEANS FOR RECEIVING INPUT SIGNALS REPRESENTATIVE OF CERTAIN DATA; CATHODE-RAY TUBE MEANS INCLUDING AT LEAST ONE VIEWING SCREEN, MEANS FOR FORMING A CATHODE-RAY BEAM IN THE TUBE AND MEANS FOR DEFLECTED THE BEAM ACROSS THE VIEWING SCREEN; MEANS COUPLED TO SAID BEAM DEFLECTING MEANS FOR PRODUCING DEFLECTION SIGNALS FOR DEFLECTING THE BEAM ACROSS SAID VIEWING SCREEN IN A PREDETERMINED MANNER TO ENABLE A SERIES OF PREDETERMINED CHARACTERS TO BE DISPLAYED ON THE VIEWING SCREEN; MEANS COUPLED TO SAID INPUT CIRCUIT MEANS AND TO SAID DEFLECTION SIGNAL PRODUCING MEANS FOR CONTROLLING THE INTENSITY OF SAID BEAM IN ACCORDANCE WITH SAID INPUT SIGNALS AND IN SYNCHRONISM WITH SAID DEFLECTION SIGNALS SELECTIVELY TO CAUSE DIFFERENT ONES OF SAID CHARACTERS TO BE DISPLAYED ON SAID SCREEN; CONVERTER CIRCUIT MEANS COUPLED TO SAID INPUT CIRCUIT MEANS FOR CONVERTING SAID INPUT SIGNALS INTO CORRESPONDING ANALOG SIGNALS; AND DISPLAY MEANS COUPLED TO SAID CON- 